By Hendrik van der Ploeg
This booklet analyses varied A/D-converter architectures with an emphasis at the greatest a possibility energy potency. It additionally offers an available assessment of the state-of-the artwork in calibration suggestions for Nyquist A/D converters. The calibration ideas provided are appropriate to different analog-to-digital platforms, similar to these utilized in built-in receivers. they permit implementation with out introducing a velocity or strength penalty.
Read or Download Calibration Techniques in Nyquist A D Converters (The International Series in Engineering and Computer Science) PDF
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Additional info for Calibration Techniques in Nyquist A D Converters (The International Series in Engineering and Computer Science)
2 Flash 29 stages after the ﬁrst interpolation stage contribute less to the total input-referred offset, resulting in a lower intrinsic capacitance. For the limit case, when the gain A0 becomes very high (∼10), only the ﬁrst interpolation stage determines the total offset. 5 for large A0 . In practice, however, the A0 is limited by the achievable linear region of the preampliﬁers and the achievable gain-bandwidth product. The pre-ampliﬁers need to be linear for a sufﬁciently large input signal swing for proper interpolation.
The pre-ampliﬁers need to be linear for a sufﬁciently large input signal swing for proper interpolation. 5 we can conclude that already for moderate gain values (A0 ∼4) the improvement in intrinsic capacitance is close to 2Nint . This improvement is caused by reducing the number of required accurate pre-ampliﬁers and therefore reducing the intrinsic capacitance. When interpolation is used with only a small gain factor, for example for very high-speed converters , the total intrinsic capacitance is not reduced.
Contrary to the two-step architecture the second stage then samples this ampliﬁed residue signal and the same operations take place. This is continued until all stages have performed their conversion. All digital output values are combined to generate the digital output code. Due to the pipelining concept (caused by the inserted SHAs) the ﬁrst stage can start sampling a new analog input signal while the second stage processes the previous sample. The speed of the conversion is therefore determined by the speed of a single stage.