By Youn-Long Steve Lin
This ebook originated from a workshop held on the DATE 2005 convention, specifically Designing complicated SOCs. cutting-edge in concerns regarding System-on-Chip (SoC) layout by means of prime specialists within the fields, it covers IP improvement, verification, integration, chip implementation, trying out and software program. It comprises helpful educational and commercial examples for these concerned with the layout of complicated SOCs.
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Additional resources for Essential Issues in SOC Design: Designing Complex Systems-on-Chip
For one current block, the search range is inputted once. Multimedia IP Development 45 SRH + N - 1 SRH + N - 1 1 SRV + N-1 N-1 N 1 N SRV + N-1 1 N-1 1 (b) (a) N SRH-1 Search Region 0 SRV + N-1 N Search Region 1 CB 0 CB 1 (c) N SRH-1 Search Region 0,1 SRV + 2N-1 CB 0 CB 2 CB 1 CB 3 N Search Region 2,3 (d) Figure 15. Data reuse schemes (a) Level A scheme (b) Level B scheme (c) Level C scheme (d) Level C+ Scheme for FSBMA, where the heavy gray region is the overlapped and reused region Level A and Level B schemes reuse the overlapped region between the reference block of the successive search candidates in the SR-level loop.
If the degree of parallelism in the tree-based architecture is only one dimension or less of current block, as shown in Figure 14 (b), the tree-based architecture is a hybrid architecture of inter-type and intra-type architectures. For example, folding the architecture in Figure 14 (a) by 2 (N) derives the architecture in Figure 14 (b). Then, it can calculate one row SAD of the search candidates in one cycle, and after generating and accumulating all row SADs in 2 (N) cycles, the total SAD of one search candidate can be derived.
However, the size of a register is the largest. Registers are more suitable for the implementation of smaller-size buffers. Memory management can be organized from two different levels: algorithmlevel and architecture-level. The embedded DRAM is one kind of circuit-level improvement. But even integrating large embedded DRAM, the access power is still larger than smaller on-chip SRAM. The algorithm-level memory hierarchy optimization is to modify the coding system algorithm to improve some system parameters, like power or area, and some other parameters, like coding performance, become the trade-off.