By Iwai H., Shur M.S., Nishi Y.
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Additional resources for Frontiers in Electronics: Proceedings of the WOFE-04
Assuming that films thinner than 3 nm can be industrially manufactured. 9 There is currently much interest on strained-Si, SiGe and Ge based MOSFETs. These technologies do not compete with SOI. They must be SOI-like. Whatever the semiconducting layer, it has to be thin and placed on an insulator in order to be applicable to extremely short MOSFETs. This is so because the electrostatic problems are more or less the same. 2. Transition from Partial to Full Depletion Partially depleted (PD) SOI MOSFETs are currently used for fabricating highend microprocessors, whereas fully depleted (FD) MOSFETs are far more suitable for advanced scaling.
In the following paragraphs, we briefly discuss our current progresses. 1. Bottom-up self-assembled nanowires Employing chemical vapor phase deposition technique, we have succeeded in growing several kinds of oxide nanowires, such as RuC>2 and ZnO nanowires of a uniform width ranging from several to few tens nm. 7 nm wide. The lattice structure is identified. -Y. Chang Fig. 1. (Prof. 2. Fabrication of four-probe electrodes With the nanowires grown and their lattice structure characterized, we have proceeded to make four-probe electrodes for electrical transport measurements.
Asano, C. Kuo, E. Anderson, T-J. King, J. Bokor, and C. Hu, "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm", IEEE Trans. Electron Devices, vol. 47, no. 12 (2000) pp. 2320-2325. F. Allibert, A. Zaslavsky, J. Pretet and S. ", Proc. ESSDERC'2001, Frontier Group (2001) pp. 267270. J. Widiez, F. Dauge, M. Vinet, T. Poiroux, B. Previtali, M. Mouis, and S. Deleonibus, "Experimental gate misalignment analysis on double gate SOI MOSFETs", IEEE Int. , Charleston, USA (2004). L. Chang, M. Ieong, and M.