Download Fully-Depleted SOI CMOS Circuits and Technology for by Takayasu Sakurai PDF

By Takayasu Sakurai

Fully-depleted SOI CMOS Circuits and expertise for Ultralow-Power functions addresses the matter of decreasing the provision voltage of traditional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit layout for FD-SOI units at a offer voltage of 1/2 V. the subjects comprise the minimal required wisdom of the fabrication of SOI substrates; FD-SOI units and the newest advancements in equipment and procedure applied sciences; and ultralow-voltage circuits, equivalent to electronic circuits, analog/RF circuits, and DC-DC converters. every one ultra-low-power strategy on the topic of units and circuits is totally defined utilizing figures to aid figuring out.

Show description

Read Online or Download Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications PDF

Best products books

Rapid Prototyping Technology

A reference and textual content encompassing crucial elements of quick prototyping know-how as a box. reports operation ideas and strategies for many strong freeform applied sciences and old platforms facts, selling layout and production tools.

Practical Oscillator Handbook

Oscillators have often been defined in books for expert wishes and as such have suffered from being inaccessible to the practitioner. This e-book takes a pragmatic strategy and offers much-needed insights into the layout of oscillators, the servicing of platforms seriously established upon them and the tailoring of useful oscillators to express calls for.

Mrp II: Planning for Manufacturing Excellence

MRP II explores the rules of MRP II structures, and the way the producer can make the most of and institute them successfully for optimum revenue. The e-book will function a precious specialist reference for brands instituting or using an MRP II scheduling process. it is going to even be a invaluable educating software for the two- and four- yr university or college courses, a reference for APICS certification overview, and carrying on with education schemes.

Optimization Methods: From Theory to Design Scientific and Technological Aspects in Mechanics

This e-book is ready optimization thoughts and is subdivided into elements. within the first half a large assessment on optimization idea is gifted. Optimization is gifted as being composed of 5 issues, particularly: layout of test, reaction floor modeling, deterministic optimization, stochastic optimization, and powerful engineering layout.

Additional resources for Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications

Example text

Flatley, “Soft Error Considerations for Deep-Submicron CMOS Circuit Applications,” IEDM Tech. Digest, pp. 315-318, 1999. 3] H. Gotou, Y. Arimoto, M. Ozeki, and K. Imaoka, “Soft Error Rate of 64k SOI-DRAM,” IEDM Tech. Digest, pp. 870-871, 1987. 4] P. K. Weimer, “The TFT – A New Thin-Film Transistor,” Proceedings of IRE, Vol. 50, pp. 1462-1469, 1962. 5] K. Maeguchi, M. Ohhashi, J. Iwamura, S. Taguchi, E. Sugino, T. Sato, and H. Tango, “4-µm LSI on SOS Using Coplanar-II Process,” IEEE Trans. on Electron Devices, Vol.

4, pp. 244-246, 1986. 11] M. Yoshimi, H. Hazama, M. Takahashi, S. Kambayashi, T. Wada, K. Kato, and H. Tango, “Two-Dimensional Simulation and Measurement on High-Perfomance MOSFET’s Made on a Very Thin SOI Film,” IEEE Trans. on Electron Devices, Vol. ED-36, No. 3, pp. 493-503, 1989. 12] M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi, M. Kemmochi, and K. Natori, “Analysis of the Drain Breakdown Mechanism in Ultra-Thin-Film SOI MOSFET’s,” IEEE Trans. on Electron Devices, Vol. ED-37, No.

As more and more accumulate, the body potential increases and the barrier height decreases, which allows more holes to flow out to the source across the barrier. Consequently, the number of holes that can accumulate in the body region is such that the number flowing out to the source balances the number generated by impact ionization. 5000/div(V) (b) Fig. 6 Drain current-voltage characteristics of (a) FD-SOI and (b) PD-SOI nMOSFETs. (From J. P. 2]. ) 32 Since a PD-SOI device has a higher potential barrier to holes than an FD-SOI device does, it allows more holes accumulate in the body region.

Download PDF sample

Rated 4.73 of 5 – based on 21 votes