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Extra resources for Resistance and Thermo-Electric Phenomena in Metal Crystals

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H. Dennard. Generalized scaling theory and its application to a micrometer MOSFET design. IEEE Trans Electron Devices. 1984; 31:452–462. 4. J. Kilby and E. Keonjian. IEDM Technical Digest. IEDM Proceedings, Washington, DC, October 29–30. 1959:76–78. 5. International Technology Roadmap of Semiconductors. http://www. net/ 6. com/press/us/en/pressrelease/ 7. be/ 8. fr/ 9. L. Clavelier, C. Deguet, L. Di Cioccio, E. Augendre, A. Brugere, P. Gueguen, Y. Le Tiec, H. Moriceau, M. Rabarot, T. Signamarcheix, J.

1 ). If needed, this VT -implant is done after the active patterning, at the same time of the well and ground plane implants. Wells are used to reduce the resistance between the body contact and the ground plane (or the substrate/BOX interface). Similarly as on bulk, the ground planes (implantation below the buried oxide) enable both the VT -adjustment and an effective body biasing. Indeed, this implanted region limits the depletion of the substrate. The gate stack is then deposited and patterned.

The superlattices are then anisotropically etched in order to pattern fins [54]. After the gate stack CVD conformal deposition the structures are subsequently planarized thanks to chemical mechanical polishing. Then, the poly-Si/TiN gate-all-around stack is etched down to the buried oxide. After gate etching, S/D implantation and spacers, S/D are then salicided and dopant atoms are activated. The fabrication ends up with a standard back-end-of-line (BEOL) process. Electrical results on the flash nanowire structure presented in Fig.

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