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By Noel M. Morris (auth.)

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11 (a). 11 is given. First, the silicon is refined into a cylindrical ingot, which is then cut up into a number of slices, each about 200 J1fT1 thick. For the purpose of comparison, the thickness of the paper on which this book is printed is about 100 Jlm. The slice forms the substrate of the I C, and is of p-type material. Vee output B E metal conductor oxide B p E buned layer ISOlatiOn moots ~ TRANSISTOR (a I ( bI Fig. 11 A monolithic integrated circuit Vcc Digital Electronic Circuits and Systems 48 An n + layer is then diffused in a special furnace into the substrate, and this layer is eventually 'buried' under an n-type epitaxial layer (meaning 'arranged upon').

7 V, which is insufficient to cause TR4 and D 1 to conduct. Had D 1 not been included, this voltage would be sufficient to maintain TR4 in a conducting state. 6 is sometimes known as a totem pole circuit because of its shape. When the output voltage is caused to change from one level to the other, both TR3 and TR4 may conduct simultaneously for a very short interval of time, resulting in a surge of current being drawn from the supply. Resistor R 4 is included to limit the value of this surge. TTL gates dominate the IC logic market, the family having three basic branches which are known as low-power, standard, and high-speed.

D. 42 The operating fan-out is an integral value, so that we would specify a fan-out of 5 for a NOR-type gate of this kind. 9(b). the fan-out is once more given by N = loutfl;n. However, we must bear in mind that the driving transistor TR2 must not only carry the current in RL, but must also ,'sink' a current of Nl;n. It is therefore possible to use a higher value of RL in the NAND circuit than is used in the NOR circuit. 9 Fan-in The fan-in of a gate refers to the maximum number of separate input lines that may be used to control the state of the gate.

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